ISA of IBM PC, Endiun Convention

ISA of IBM PC
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The Processor
The processor is partitioned into two logical units: an Execution Unit (EU) and a Bus Interface Unit (BIU). The role of the EU is to execute instructions, whereas the BIU delivers instructions and data to the EU. The EU contains ALU, a control unit and a number of registers. These features provide for execution of instructions and arithmetic and logic operations. The BIU controls the buses that transfer data to the EU, to memory, and to I/O devices. It also manages segment registers and instruction queue. Segment registers control memory addressing and will be described shortly. Instructions fetched from main memory by BIU are placed in an instruction queue, which varies in size depending on the processor. This feature enables fetching of instructions in parallel with instruction execution and hence results in speeding up execution.
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Memory Addressing
Depending on the machine, a processor can access one or more bytes from memory at a time. The number of bytes accessed simultaneously from main memory is called word length of machine. Generally, all machines are byte-addressable i.e.; every byte stored in memory has a unique address. However, word length of a machine is typically some integral multiple of a byte. Therefore, the address of a word must be the address of one of its constituting bytes. In this regard, one of the following methods of addressing may be used. 

Big Endian:
 The word address is taken as the address of the most significant byte in the word. MIPS, Apple Macintosh are some of the machines in this class. 


Little Endian:
 Here the word address is taken as the address of the least significant byte in the word. Intel’s machines are of this type. Consider for example, storing hex number 245A in main memory. The least significant byte 5A will be stored in low memory address and most significant byte 24 will be stored in high memory address.